`timescale	1ps/1ps
module a3_mcu_top(
		//时钟和复位
                input	wire		resetb,
                input   wire		sclk,
                
		//jtag接口
		input	wire		JTCK,
		input	wire		JTDI,
		input	wire		JTMS,
		output	wire		JTDO,

		//flash接口
		output	wire		flash_CS_n,
		output	wire		flash_SCK,
		output	wire		flash_SI,
		input	wire		flash_SO,

		//内部配置总线
		output	wire		set_d_ok,
		output	wire	[31:0]	set_addr,
		output	wire	[7:0]	set_data,
		output	wire		set_r_req,
		input	wire	[7:0]	set_rdata,
		
		//GPIO
		inout	tri	[7:0]	mcu_port_a,

		//调试信号
		output	wire	[31:0]	tout
		);

//**********************************************/
//        	信号定义
/***********************************************/
reg		mcu_clk;
wire	[1:0]	hresp, htrans;
wire	[2:0]	hsize;
wire		hwrite, hsel, hready_out, hready_in;
wire	[31:0]	haddr, hwdata, hrdata;

wire	[7:0]	GPIO0_I, GPIO0_O, nGPEN0;
wire	[7:0]	GPIO1_I, GPIO1_O, nGPEN1;
wire	[7:0]	GPIO2_I, GPIO2_O, nGPEN2;

wire	[31:0]	core_tout;

//**********************************************/
//        	mcu时钟
/***********************************************/
always @(posedge sclk)
	mcu_clk <= ~mcu_clk;

//**********************************************/
//        	mcu相关模块
/***********************************************/
//MCU内核
mcu_agm_core    mcu_core(
		//时钟和复位
    		.resetb			(resetb),
		.mcu_clk		(mcu_clk),
 
		//JTAG调试
    		.JTCK                   (JTCK),
    		.JTDI                   (JTDI),
    		.JTMS			(JTMS),
    		.JTDO                   (JTDO),
 
		//Flash接口
    		.FLASH_BIAS             (24'hB1CE6),
    		.FLASH_CS_n             (flash_CS_n),
		.FLASH_SCK              (flash_SCK),
    		.FLASH_SI		(flash_SI),
    		.FLASH_SO		(flash_SO),

		//共享RAM接口
    		.EXT_RAM_EN             (EXT_RAM_EN),
    		.EXT_RAM_WR             (EXT_RAM_WR),
    		.EXT_RAM_ADDR           (EXT_RAM_ADDR),
    		.EXT_RAM_BYTE_EN        (EXT_RAM_BYTE_EN),
    		.EXT_RAM_WDATA          (EXT_RAM_WDATA),
    		.EXT_RAM_RDATA          (EXT_RAM_RDATA),
 
		//AHB接口
    		.htrans			(htrans),
    		.hsize			(hsize),
		.hsel			(hsel),
		.hwrite			(hwrite),
    		.haddr			(haddr),
		.hwdata			(hwdata),
    		.hrdata			(hrdata),
   		.hresp			(hresp),
    		.hready			(hready_out),

  		//串口
   		.UART_RXD               (),
    		.UART_TXD               (),

  		//GPIO
    		.GPIO0_I                (GPIO0_I),
    		.GPIO0_O                (GPIO0_O),
    		.nGPEN0                 (nGPEN0),
    		.GPIO1_I                (GPIO1_I),
    		.GPIO1_O                (GPIO1_O),
    		.nGPEN1                 (nGPEN1),
    		.GPIO2_I                (GPIO2_I),
    		.GPIO2_O                (GPIO2_O),
    		.nGPEN2                 (nGPEN2),
    		
    		.tout               	(core_tout)
		);

//**************************************************************
//        		GPIO输出
//**************************************************************
assign	mcu_port_a[0] = (nGPEN0[0] == 1)? 	GPIO0_O[0]	:1'bz;
assign	mcu_port_a[1] = (nGPEN0[1] == 1)? 	GPIO0_O[1]	:1'bz;
assign	mcu_port_a[2] = (nGPEN0[2] == 1)? 	GPIO0_O[2]	:1'bz;
assign	mcu_port_a[3] = (nGPEN0[3] == 1)? 	GPIO0_O[3]	:1'bz;
assign	mcu_port_a[4] = (nGPEN0[4] == 1)? 	GPIO0_O[4]	:1'bz;
assign	mcu_port_a[5] = (nGPEN0[5] == 1)? 	GPIO0_O[5]	:1'bz;
assign	mcu_port_a[6] = (nGPEN0[6] == 1)? 	GPIO0_O[6]	:1'bz;
assign	mcu_port_a[7] = (nGPEN0[7] == 1)? 	GPIO0_O[7]	:1'bz;

assign	GPIO0_I = mcu_port_a;

//**************************************************************
//        		调试信号
//**************************************************************
assign tout = core_tout;

endmodule
